ABRT_SLVFLUSH_TXFIFO=ABRT_SLVFLUSH_TXFIFO_VOID, ABRT_USER_ABRT=ABRT_USER_ABRT_VOID, ABRT_SLV_ARBLOST=ABRT_SLV_ARBLOST_VOID, ABRT_HS_ACKDET=ABRT_HS_ACK_VOID, ABRT_10B_RD_NORSTRT=ABRT_10B_RD_VOID, ABRT_SBYTE_NORSTRT=ABRT_SBYTE_NORSTRT_VOID, ABRT_MASTER_DIS=ABRT_MASTER_DIS_VOID, ABRT_SLVRD_INTX=ABRT_SLVRD_INTX_VOID, ABRT_GCALL_NOACK=ABRT_GCALL_NOACK_VOID, ABRT_7B_ADDR_NOACK=INACTIVE, ABRT_10ADDR2_NOACK=INACTIVE, ABRT_SBYTE_ACKDET=ABRT_SBYTE_ACKDET_VOID, ABRT_TXDATA_NOACK=ABRT_TXDATA_NOACK_VOID, ABRT_HS_NORSTRT=ABRT_HS_NORSTRT_VOID, ARB_LOST=ABRT_LOST_VOID, ABRT_GCALL_READ=ABRT_GCALL_READ_VOID, ABRT_10ADDR1_NOACK=INACTIVE
I2C Transmit Abort Source Register
This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.
| ABRT_7B_ADDR_NOACK | This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0 (INACTIVE): This abort is not generated 1 (ACTIVE): This abort is generated because of NOACK for 7-bit address |
| ABRT_10ADDR1_NOACK | This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0 (INACTIVE): This abort is not generated 1 (ACTIVE): Byte 1 of 10Bit Address not ACKed by any slave |
| ABRT_10ADDR2_NOACK | This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0 (INACTIVE): This abort is not generated 1 (ACTIVE): Byte 2 of 10Bit Address not ACKed by any slave |
| ABRT_TXDATA_NOACK | This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter 0 (ABRT_TXDATA_NOACK_VOID): Transmitted data non-ACKed by addressed slave-scenario not present 1 (ABRT_TXDATA_NOACK_GENERATED): Transmitted data not ACKed by addressed slave |
| ABRT_GCALL_NOACK | This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter 0 (ABRT_GCALL_NOACK_VOID): GCALL not ACKed by any slave-scenario not present 1 (ABRT_GCALL_NOACK_GENERATED): GCALL not ACKed by any slave |
| ABRT_GCALL_READ | This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter 0 (ABRT_GCALL_READ_VOID): GCALL is followed by read from bus-scenario not present 1 (ABRT_GCALL_READ_GENERATED): GCALL is followed by read from bus |
| ABRT_HS_ACKDET | This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master 0 (ABRT_HS_ACK_VOID): HS Master code ACKed in HS Mode- scenario not present 1 (ABRT_HS_ACK_GENERATED): HS Master code ACKed in HS Mode |
| ABRT_SBYTE_ACKDET | This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master 0 (ABRT_SBYTE_ACKDET_VOID): ACK detected for START byte- scenario not present 1 (ABRT_SBYTE_ACKDET_GENERATED): ACK detected for START byte |
| ABRT_HS_NORSTRT | This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0 (ABRT_HS_NORSTRT_VOID): User trying to switch Master to HS mode when RESTART disabled- scenario not present 1 (ABRT_HS_NORSTRT_GENERATED): User trying to switch Master to HS mode when RESTART disabled |
| ABRT_SBYTE_NORSTRT | To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master 0 (ABRT_SBYTE_NORSTRT_VOID): User trying to send START byte when RESTART disabled- scenario not present 1 (ABRT_SBYTE_NORSTRT_GENERATED): User trying to send START byte when RESTART disabled |
| ABRT_10B_RD_NORSTRT | This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver 0 (ABRT_10B_RD_VOID): Master not trying to read in 10Bit addressing mode when RESTART disabled 1 (ABRT_10B_RD_GENERATED): Master trying to read in 10Bit addressing mode when RESTART disabled |
| ABRT_MASTER_DIS | This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0 (ABRT_MASTER_DIS_VOID): User initiating master operation when MASTER disabled- scenario not present 1 (ABRT_MASTER_DIS_GENERATED): User initiating master operation when MASTER disabled |
| ARB_LOST | This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter 0 (ABRT_LOST_VOID): Master or Slave-Transmitter lost arbitration- scenario not present 1 (ABRT_LOST_GENERATED): Master or Slave-Transmitter lost arbitration |
| ABRT_SLVFLUSH_TXFIFO | This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter 0 (ABRT_SLVFLUSH_TXFIFO_VOID): Slave flushes existing data in TX-FIFO upon getting read command- scenario not present 1 (ABRT_SLVFLUSH_TXFIFO_GENERATED): Slave flushes existing data in TX-FIFO upon getting read command |
| ABRT_SLV_ARBLOST | This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never ‘owns’ the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter 0 (ABRT_SLV_ARBLOST_VOID): Slave lost arbitration to remote master- scenario not present 1 (ABRT_SLV_ARBLOST_GENERATED): Slave lost arbitration to remote master |
| ABRT_SLVRD_INTX | 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter 0 (ABRT_SLVRD_INTX_VOID): Slave trying to transmit to remote master in read mode- scenario not present 1 (ABRT_SLVRD_INTX_GENERATED): Slave trying to transmit to remote master in read mode |
| ABRT_USER_ABRT | This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter 0 (ABRT_USER_ABRT_VOID): Transfer abort detected by master- scenario not present 1 (ABRT_USER_ABRT_GENERATED): Transfer abort detected by master |
| TX_FLUSH_CNT | This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter |